1. Technical Field
Embodiments of the invention relate generally to Analog to Digital Converters (ADCs) and more particularly to methods and systems for designing high resolution ADCs.
2. Discussion of Prior Art
Analog to Digital Converters (ADCs) serve to translate a given analog input signal (over a given range of potential signal values) into a corresponding digital signal. The prior art is replete with a host of different types of ADC architectures. They include, for example, flash architecture, pipelined architecture, successive approximation architecture and sigma delta architecture.
A pipelined ADC divides an analog-to-digital conversion task into several consecutive stages, namely, a sample and hold stage, followed by one or more pipeline stages, and finally a flash stage. The sample and hold stage samples and holds the analog input signal. It is followed by a set of pipelined stages. Each pipelined stage produces a digital estimate of an analog held signal received at an input of the stage. More particularly, at each pipelined stage, a digital estimate of the analog held signal is calculated, the digital estimate is then converted back to an analog waveform and is subtracted from the analog held signal received at the input of the stage. The result of the subtraction is referred to as residue value. The residual analog signal is then amplified in the hold phase and supplied to the next stage in the pipeline to be sampled and converted in an identical manner.
Each of the pipelined stages is constructed in an identical manner. That is, each includes a sample and hold circuit, an ADC, and a Digital to Analog (D/A) converter (DAC). The ADC uses two clock phases, namely, a sample phase and a hold phase for Analog to Digital (A/D) conversion. The sample phase is used to sample the input signal on the sampling capacitors. The input analog signal is the output voltage from the previous stage. For the hold phase, the input signal is the analog voltage which is supplied as an input to the ADC. The hold phase is used to calculate the residue value. The sampled input analog signal is subtracted from the nearest DAC value determined by the comparator array. The subtracted output is commonly referred to as residue value. The residual analog signal is then amplified in the hold phase and supplied to the next stage in the pipeline to be sampled and converted in an identical manner to stage 1. This process is repeated through as many stages as are necessary to achieve a desired resolution.
In conventional pipelined ADCs, errors created in one stage are propagated to the later stages. These errors are the key reason for reducing the performance of the ADC. Mainly there are two types of errors which reduce the performance of the ADC, namely gain error and reference voltage error. If the gain of the residue amplifier of a stage varies from the desired gain, there is a gain error in the residue amplifier which affects the residue value output of that particular stage.
Pipelined ADC requires a reference voltage to convert the analog input voltage into digital data. Given an input voltage sample Vin, the ADC output is D (a digital data) such that, Vin=D*Vref+Qer; where ‘Vref’ is the reference voltage and Qer is the quantization error. ‘Vref’ is used in every stage of a pipelined ADC to extract the bits. A simplified diagram of a typical pipeline stage is illustrated in FIG. 1, 100.
In FIG. 1, in the sample phase of the clock, the sampling capacitors 105 sample the input voltage ‘Vin’. In the hold phase of the clock, ‘Vin’ is subtracted from the nearest Digital to Analog Converter (DAC) value. A stage having ‘n’ number of DAC values has ‘n’ number of unit sampling capacitors 105. Depending on the comparator code, ‘m’ number of them are connected to ‘Vref’ in the hold phase, rest of the ‘n-m’ number of capacitors are connected to ground. The equivalent DAC value implemented is (m/n)*Vref. Charge drawn from the reference is m*C*(Vin−Vref), where ‘C’ is the unit sampling capacitance.
This charge is stored in the feedback capacitor 120 of the corresponding stage. The output voltage of the stage is Vres=G (Vin−Vref);                Where, the gain of the residue amplifier, G=m*C/Cf, and        Cf=feedback capacitance.        
This voltage is called the residue value of the corresponding stage and is used as the input voltage to the next stage to extract the following sets of bits. Error in residue value results in erroneous decision in the following stage and affects the digital code output of the entire ADC stages.
At the hold phase, the reference voltage, Vref dips due to the finite output impedance to supply the charge to the sampling capacitors 105. If the dip (or reference voltage error) in the reference voltage is ‘Ve’, the resultant error in residue value is Ver_res=−G*Ve. To reduce this reference voltage error, Ve needs to be reduced. To reduce Ve, the output impedance of the reference voltage Vref has to be reduced. To reduce the error in reference voltage, Vref to ¼LSB (Least Significant Bit) (480 uV) of a 12-bit ADC having IV reference voltage and 2 pF sampling capacitance at stage 1, the output impedance needs to be less than 1 ohm. This low output impedance across frequency is difficult to obtain, if not impossible, especially considering the reference voltage routing to every stages.
Most of the available ADCs today have a resolution of 8 bits. Relative to a 12-bit ADC, an 8-bit ADC has 1/16th the resolution. In addition, the input sampling capacitance can be considerably reduced, as a result, the tolerable error in reference voltage is 16-times higher than that of an 8-bit converter and hence the effective output impedance can be as high as 16 ohm. However, such moderate output impedances are not acceptable in high resolution ADCs with 12 or more number of bits. There are several methods in the art for correcting these errors in the ADC in the digital domain. These methods are time consuming and cannot perform error correction in analog domain.
Hence, it would be advantageous to have a system and method for eliminating the gain error and reference voltage error in an ADC in the analog domain, thereby increasing the resolution of the ADC.